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PD-95331
AUTOMOTIVE MOSFET
Typical Applications
Electric Power Steering (EPS) Anti-lock Braking System (ABS) Wiper Control Climate Control Power Door Lead-Free
IRF1405SPbF IRF1405LPBF
HEXFET(R) Power MOSFET
D
VDSS = 55V
G S
Benefits
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax
RDS(on) = 5.3m ID = 131A
Description
Stripe Planar design of HEXFET(R) Power MOSFETs utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
D2Pak IRF1405S
TO-262 IRF1405L
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
Max.
131 93 680 200 1.3 20 590 See Fig.12a, 12b, 15, 16 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB mount)
Typ.
--- ---
Max.
0.75 40
Units
C/W
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1
05/27/04
IRF1405S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff.
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. 55 --- --- 2.0 69 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.057 4.6 --- --- --- --- --- --- 170 44 62 13 190 130 110 4.5 7.5 5480 1210 280 5210 900 1500
Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 5.3 m VGS = 10V, ID = 101A 4.0 V VDS = 10V, ID = 250A --- S VDS = 25V, ID = 110A 20 VDS = 55V, VGS = 0V A 250 VDS = 44V, VGS = 0V, TJ = 150C 200 VGS = 20V nA -200 VGS = -20V 260 ID = 101A 66 nC VDS = 44V 93 VGS = 10V --- VDD = 38V --- ID = 110A ns --- RG = 1.1 --- VGS = 10V D Between lead, --- 6mm (0.25in.) nH G from package --- and center of die contact S --- VGS = 0V --- pF VDS = 25V --- = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 44V, = 1.0MHz --- VGS = 0V, VDS = 0V to 44V
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 131 showing the A G integral reverse --- --- 680 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 101A, VGS = 0V --- 88 130 ns TJ = 25C, IF = 101A --- 250 380 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF1405S/LPbF
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
I D , Drain-to-Source Current (A)
100
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
10
4.5V
20s PULSE WIDTH TJ = 25 C
1 10 100
4.5V
20s PULSE WIDTH TJ = 175 C
1 10 100
1 0.1
10 0.1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
TJ = 175 C
RDS(on) , Drain-to-Source On Resistance (Normalized)
TJ = 25 C
ID = 169A
I D , Drain-to-Source Current (A)
2.5
100
2.0
1.5
10
1.0
0.5
1 4 6 8
V DS = 25V 20s PULSE WIDTH 10 12
0.0 -60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF1405S/LPbF
100000
20
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + C ds gd
ID = 101A VDS = 44V VDS = 27V
16
C, Capacitance(pF)
10000
Ciss
12
Coss
1000
8
Crss
4
100 1 10 100
0 0 60 120
FOR TEST CIRCUIT SEE FIGURE 13
180 240 300
VDS, Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
TJ = 175 C
100
I D , Drain Current (A)
1000 10us 100us 1ms 10 10ms
100
TJ = 25 C
10
1 0.0
V GS = 0 V
0.5 1.0 1.5 2.0 2.5 3.0
1 1
TC = 25 C TJ = 175 C Single Pulse
10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF1405S/LPbF
160
LIMITED BY PACKAGE
VDS VGS
RD
I D , Drain Current (A)
120
RG 10V
D.U.T.
+
-VDD
80
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
40
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1 D = 0.50
Thermal Response (Z thJC )
0.20 0.1 0.10 0.05 0.02 0.01
0.01
SINGLE PULSE (THERMAL RESPONSE)
PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC
0.001 0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF1405S/LPbF
EAS , Single Pulse Avalanche Energy (mJ)
15V
1400 1200 1000 800 600 400 200 0 25 50 75 100
VDS
L
DRIVER
ID 41A 71A BOTTOM 101A TOP
RG
20V
D.U.T
IAS tp
+ - VDD
A
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
125
150
175
Starting TJ , Junction Temperature ( C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG
3.5
QGD
4.0
Charge
VGS(th) , Variace ( V )
3.0
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
ID = 250A
2.5
50K 12V .2F .3F
2.0
D.U.T. + V - DS
1.5
VGS
3mA
-75 -50 -25
0
25
50
75
100 125 150 175
T J , Temperature ( C )
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
6
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IRF1405S/LPbF
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01 0.05
10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses
0.10
1
0.1 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
600
EAR , Avalanche Energy (mJ)
500
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 101A
400
300
200
100
0 25 50 75 100 125 150 175
Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*t av
Fig 16. Maximum Avalanche Energy Vs. Temperature
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IRF1405S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG VGS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ VDD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 17. For N-channel HEXFET(R) power MOSFETs
8
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IRF1405S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF 530S WIT H L OT CODE 8024 AS S E MB L E D ON WW 02, 2000 IN T HE AS S E MB L Y L INE "L " Note: "P" in as s embly line pos ition indicates "L ead-F ree" INT E RNAT IONAL RE CT IF IER L OGO AS S E MB L Y L OT CODE PART NUMB E R F 530S DAT E CODE YE AR 0 = 2000 WEE K 02 L INE L
OR
INT E RNAT IONAL RECT IF IER L OGO AS S E MB L Y LOT CODE PART NU MB ER F530S DAT E CODE P = DE S IGNAT E S LE AD-F RE E PR ODU CT (OPT IONAL ) YEAR 0 = 2000 WE EK 02 A = AS S EMB LY S IT E CODE
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IRF1405S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 ASSEMB LED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNATIONAL RECTIF IER LOGO ASSEMBLY LOT CODE PART NUMBER
DATE CODE YE AR 7 = 1997 WEE K 19 LINE C
OR
INTERNATIONAL RECT IF IER LOGO PART NUMBER DAT E CODE P = DESIGNATES LEAD-F REE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SIT E CODE
AS SEMBLY LOT CODE
10
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IRF1405S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11). Starting TJ = 25C, L = 0.11mH RG = 25, IAS = 101A. (See Figure 12). ISD 101A, di/dt 210A/s, VDD V(BR)DSS, TJ 175C Pulse width 400s; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.05/04
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11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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